1. Field
This invention relates generally to radio frequency (RF) receivers, and more specifically to direct current (DC) offset correction in a receiver with an automatic gain control.
2. Related Art
A DC offset is a voltage that may appear at an output of a mixer of a zero intermediate frequency (IF) receiver in the absence of a received signal. The DC offset can be caused by leakage current from a local oscillator to the mixer of the zero-IF receiver. The DC offset is added to, and becomes an unwanted part of, the received signal. The DC offset is of concern in receivers that are implemented substantially in integrated circuit form because techniques to mitigate the DC offset, such as suitable blocking capacitors, are not readily available in integrated circuits. Baseband DC offset correction is commonly used in zero-IF receivers to reduce or eliminate DC offsets. Elimination of the DC offset is desirable to avoid clipping within the baseband analog signal path as well as to meet a desired receiver performance, e.g., receiver sensitivity, under weaker signal conditions.
A critical receiver performance metric used for high-speed downlink packet access (HSDPA or 3.5 G) transceivers is the receiver error vector magnitude (EVM) performance under both on-channel signal-only and interferer test cases. HSDPA transceivers require a receiver EVM of around 5% to achieve desired network throughput at signal levels of −60 dBm and higher. Receiver EVM performance is typically required to be 5% under on-channel signal-only test cases at antenna signal levels of −60 dBm and higher. Receiver EVM performance is typically required to be approximately 10% for adjacent channel interferer test cases.
To achieve this type of receiver EVM performance, a DC notch, i.e., a high-pass notch, in the receiver of 1-kHz or less should be maintained. This requirement causes a fine DC offset correction filter or system, and a digital automatic gain control (DAGC) unit, in such receivers to maintain loop bandwidths of 1-kHz or less. Maintenance of such narrow DC notch bandwidths in the fine DC offset correction filter or system, and in the DAGC unit, causes the receiver to be unable to quickly track out large DC and gain errors introduced in the receiver whenever an RF/IF AGC system of the receiver alters RF and/or baseband gain settings. This inability leads to degraded receiver performance under fading channel conditions. The receiver EVM is significantly degraded when the DC notch in the receiver is increased beyond approximately 1-kHz. Furthermore, running the fine DC offset correction system and the DAGC unit continuously in a medium or high bandwidth mode of operation significantly degrades receiver EVM performance to an unacceptably large degree of more than 15%.
Known receivers lack the ability to both maintain a narrow DC notch (e.g., <1-kHz) in the receiver to optimize performance, such as EVM, under static channel conditions, and to dynamically alter the DC notch under fading channel conditions to optimize performance, such as block error rate, under fading channel conditions.
Most known DC offset correction techniques focus on methods for coarse DC offset correction. Known methods and apparatus focus on methods for mixed-signal coarse DC correction applied within the receive analog signal path. Known methods do not consider the interaction between RF/IF AGC, coarse DC offset correction, and fine DC offset correction systems, to continuously maintain a narrow fine DC offset correction notch in a receiver. Known methods do not consider interactions required between RF/IF AGC and digital AGC systems to maintain a low bandwidth in the digital AGC system. Known methods do not minimize the DC notch (e.g., due to fine DC offset correction and digital AGC systems) in receivers supporting continuous data reception, such as in HSDPA and wideband code division multiple access (WCDMA) systems.
An HSDPA system requires a frequency response that is relatively flat for any signal components greater than 1-kHz (thereby setting a maximum loop bandwidth of a DC offset correction system) in order to ensure a desired EVM performance. The HSPDA system and other systems, such as WCDMA and enhanced global packet radio systems, can require receiver warm-up times (i.e., the time until the receiver is providing accurately demodulated data) that are less than 100-μsec, which establishes a response time constraint for the DC offset correction system. Furthermore, if the receiver needs to track fading in the RF signal, the required response times may be even shorter.